Efficient LDPC Decoder Implementation for DVB-S2 System

被引：0
|
作者：
Tsai, Chung-Jin
Chen, Mu-Chung
机构：
来源：
2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT) | 2010年
关键词：
Low Density Parity Check (LDPC) codes; LDPC decoder; compensation architecture; normalization; early termination; shrinking;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Low Density Parity Check (LDPC) codes have been adopted in many communication standards in recent years due to their Shannon limit approaching performance. More than that, many standards adopt long block length LDPC codes to achieve better performance. Calculation units are, therefore, increased significantly. Traditional simplified algorithm is not suitable for cutting edge transmission of high quality multimedia data because of the serious performance degradation. Better performance with minimum compensation architecture must be realized. This paper is to present the compensation architecture with minimum added circuits.
引用
收藏
页码：37 / 40
页数：4
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