A synthesizable IP core for DVB-S2 LDPC code decoding

被引：53
|
作者：
Kienle, F [1 ]
Brack, T [1 ]
Wehn, N [1 ]
机构：
[1] Univ Kaiserslautern, Microelect Syst Design Res Grp, D-67663 Kaiserslautern, Germany
来源：
DESIGNERS' FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION | 2005年
关键词：
D O I：
10.1109/DATE.2005.39
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size of 64800 which allows a transmission close to the theoretical limits. The decoding of LDPC is an iterative process. For DVB-S2 about 300000 messages are processed and reordered in each of the 30 iterations. These huge data processing and storage requirements are a real challenge for the decoder hardware realization, which has to fulfill the specified throughput of 255MBit/s for base station applications. In this paper we will show, to the best of our knowledge, the first published IP LDPC decoder core for the DVB-S2 standard. We present a synthesizable IP block based on ST Microelectronics 0.13 mu m CMOS technology.
引用
收藏
页码：100 / 105
页数：6
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