A New Seven Level Symmetric Inverter with Reduced Number of Switches and DC Sources

被引:0
|
作者
Balamurugan, M. [1 ]
Prakash, Gnana M. [1 ]
Umashankar, S. [1 ]
机构
[1] VIT Univ, Sch Elect Engn, Vellore, Tamil Nadu, India
关键词
Multilevel inverters; PWM technique; Total harmonic distortion;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This Multilevel inverter technology has recently become known has a very important substitute in the area of high power medium voltage energy control. Though multilevel inverter has several advantages it has drawbacks like for higher levels more number of semiconductor switches needed this may lead to huge size and cost of the inverter is very high. So in order to overcome this problem a new multilevel inverter is proposed with reduced number of switches. The proposed topology has three Dc sources and six Switches and it is well suited for high power applications. Level shifted PWM technique is used to generate the sine wave for the proposed topology. The Circuit is simulated in Matlab/Simulink and effect of harmonic spectrum is analyzed through the Fast Fourier transform window. The performance parameters of the proposed multilevel inverter are compared with the conventional MLI and another seven level existing topologies.
引用
收藏
页数:6
相关论文
共 50 条
  • [41] A new multi-level inverter with reduced number of switches based on modified H-bridge
    Annamalai T.
    Udhayakumar K.
    [J]. International Journal of Power Electronics, 2019, 10 (1-2) : 49 - 64
  • [42] A Multilevel Inverter Topology With Reduced Number of Switches
    Kashif, Muhammad Fayyaz
    Rashid, Amir Khurrum
    [J]. 2016 INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS ENGINEERING (ICISE), 2016, : 268 - 271
  • [43] A New Bridgeless Multilevel Inverter Structure with Reduced Number of Power Switches
    Bektas, Enes
    Bayindir, Kamil Cagatay
    Karaca, Hulusi
    [J]. 2017 10TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONICS ENGINEERING (ELECO), 2017, : 300 - 304
  • [44] New Single Phase Multilevel Inverter Topology with Reduced Number of Switches
    Malathy, S.
    Ramaprabha, R.
    [J]. 2016 3RD INTERNATIONAL CONFERENCE ON ELECTRICAL ENERGY SYSTEMS (ICEES), 2016, : 139 - 144
  • [45] Design of Multilevel Inverter with Reduced Number of Switches
    Shimpi, A.
    Sheikh, A.
    Bhil, S.
    [J]. 2020 7TH INTERNATIONAL CONFERENCE ON CONTROL, DECISION AND INFORMATION TECHNOLOGIES (CODIT'20), VOL 1, 2020, : 1203 - 1208
  • [46] Design of new asymmetrical cascaded multilevel inverter with reduced number of switches
    Bharathi C.R.
    [J]. European Journal of Electrical Engineering, 2019, 21 (06) : 547 - 552
  • [47] A New Topology of Multilevel Inverter with Reduced Number of Switches and Increased Efficiency
    Sukanya, V
    Mukundan, Nirmal C. M.
    Jayaprakash, P.
    Asokan, O., V
    [J]. 2018 IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS (PEDES), 2018,
  • [48] New Asymmetrical Modular Multilevel Inverter Topology With Reduced Number of Switches
    Kakar, Saifullah
    Ayob, Shahrin Bin Md.
    Iqbal, Atif
    Nordin, Norjulia Mohamad
    Bin Arif, M. Saad
    Gore, Sheetal
    [J]. IEEE ACCESS, 2021, 9 : 27627 - 27637
  • [49] Fuzzy Logic Controller for Nine Level Multi-Level Inverter with Reduced Number of Switches
    Madhav, Leela K.
    Babu, Challa
    Ponnambalam, P.
    Mahapatra, Ashutos
    [J]. 2017 INNOVATIONS IN POWER AND ADVANCED COMPUTING TECHNOLOGIES (I-PACT), 2017,
  • [50] A Seven Level Cascaded H-Bridge Inverter Topology with Reduced Sources
    Sahoo, Rajanikanta
    Kasari, Prabir Ranjan
    Mishra, Manas Ranjan
    Chakraborti, Abanishwar
    Kumar, Ambati Dinesh
    Das, Bikram
    [J]. PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON INVENTIVE SYSTEMS AND CONTROL (ICISC 2018), 2018, : 655 - 660