A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

被引：0
|
作者：
Newbould, RD [1 ]
Carothers, JD [1 ]
Rodriguez, JJ [1 ]
Holman, WT [1 ]
机构：
[1] Univ Arizona, Dept Elect & Comp Engn, Tucson, AZ 85721 USA
来源：
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.
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页码：862 / 865
页数：4
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