A 0.9V 12-bit 200-kS/s 1.07μW SAR ADC with Ladder-based Reconfigurable Time-Domain Comparator

This paper presents a SAR ADC for biomedical application, which has a strict limit on its power consumption. Thus, two techniques are introduced into its design: a novel ladder-based reconfig-urable time domain (RTD) comparator is proposed to reduce the noise and to adjust power according to inputs automatically; and a novel clock distribution circuit is utilized to save more than 55% power consumption. The prototype chip is designed and fabricated in UMC 0.18 mu m technology. The simulation results show that with supply voltage of 0.9V, the ADC consumes 1.07 mu W at the sampling rate of 200kS/s. And the SNDR is 71.2 dB with 3.24kHz input sinusoid signal, showing the corresponding figure-of-merit of 1.8 fJ /conversion-step.