A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator

被引：0

作者：

杨思宇 ^{[1
]}

张辉 ^{[1
]}

付文汇 ^{[1
]}

易婷 ^{[1
]}

洪志良 ^{[1
]}

机构：

[1] State Key Laboratory of ASIC and System,Fudan University

来源：

Journal of Semiconductors | 2011年 / 32卷 / 03期

基金：

中国国家自然科学基金;

关键词：

successive approximation register; A/D; differential time domain comparator;

D O I：

暂无

中图分类号：

TN792 [];

学科分类号：

080902 ;

摘要：

A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.

引用

页码：88 / 93

页数：6

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