Design-for-testability for improved path delay fault coverage of critical paths

The path delay fault coverage achievable for a circuit may be low even when enhanced scan is available and only, faults associated with critical paths are considered. To address this issue we describe a design-for-testability (DFT) approach that targets the critical (or longest) paths of the circuit. In a basic step of the proposed procedure, a fanout branch that is not on a longest path is disconnected from its stem, and driven from a new input in order to reduce the dependencies between off-path inputs of a target path delay fault. We present experimental results to demonstrate the increase in fault coverage of faults associated with longest paths as the number of new inputs is increased. We also discuss the implementation of the DFT approach in the context of scan design.