Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application

A new methodology is developed in this paper for identifying possible path delay faults through at-speed resting of sequential non-scan circuits. In the past, different techniques have been proposed for diagnosing delay faults in sequential circuits through variable clock control techniques. These techniques are, however not readily applicable to commercial high-performance ICs. We propose new techniques based on critical-path tracing which can be used to locate slow paths in sequential circuits. Strategies have been developed to improve the diagnostic resolution, which involve deducing internal state values from the observed circuit outputs and the detection of fault-free circuit paths. Results of experiments on the ISCAS89 sequential benchmark suite are finally discussed.