Test sequence compaction for sequential circuits with reset states

被引:1
|
作者
Higami, Y [1 ]
Takamatsu, Y [1 ]
Kinoshita, K [1 ]
机构
[1] Ehime Univ, Matsuyama, Ehime 790, Japan
关键词
D O I
10.1109/ATS.2000.893620
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a static test compaction method for sequential circuits with reset states under single stuck-at fault assumption. The proposed method first finds unremovable vectors by fault-dropping fault simulation or by non-fault-dropping fault simulation. Next, a subset of test vectors other than unremovable vectors are replaced with a reset signal. Detection of faults detected by an original test sequence is guaranteed by logic simulation and fault simulation for test subsequences. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method.
引用
收藏
页码:165 / 170
页数:6
相关论文
共 50 条
  • [41] Specification test compaction for analog circuits and MEMS
    Biswas, S
    Li, P
    Blanton, RD
    Pileggi, LT
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 164 - 169
  • [42] Test set compaction algorithms for combinational circuits
    Hamzaoglu, I
    Patel, JH
    [J]. 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 283 - 289
  • [43] Test set compaction algorithms for combinational circuits
    Hamzaoglu, I
    Patel, JH
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2000, 19 (08) : 957 - 963
  • [44] Testability and test compaction for decision diagram circuits
    Bystrov, A
    Almaini, AEA
    [J]. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1999, 146 (04): : 153 - 158
  • [45] TEST SET COMPACTION FOR COMBINATIONAL-CIRCUITS
    CHANG, JS
    LIN, CS
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (11) : 1370 - 1378
  • [46] Identifying legal and illegal states in synchronous sequential circuits using test generation
    Bareisa, E
    Motiejunas, K
    Seinauskas, R
    [J]. INFORMATICA, 2003, 14 (02) : 135 - 154
  • [47] A new approach to test generation and test compaction for scan circuits
    Pomeranz, I
    Reddy, SM
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 1000 - 1005
  • [48] COREL: A dynamic compaction procedure for synchronous sequential circuits with repetition and local static compaction
    Pomeranz, I
    Reddy, SM
    [J]. 2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 2001, : 142 - 147
  • [49] Diagnostic test generation for sequential circuits
    Yu, XM
    Wu, J
    Rudnick, EM
    [J]. INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 225 - 234
  • [50] THE PSEUDOEXHAUSTIVE TEST OF SEQUENTIAL-CIRCUITS
    WUNDERLICH, HJ
    HELLEBRAND, S
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1992, 11 (01) : 26 - 33