Testability and test compaction for decision diagram circuits

Novel node realisations are used to represent reduced ordered binary, functional and Kronecker decision diagrams as irredundant combinational circuits. These types of decision diagrams are compact and able to represent very large switching functions. The resulting circuits are completely testable in the single and multiple stuck-at fault models. Theorems on diagnostic properties of these circuits are formulated. The high complexity of functions represented by decision diagram circuits calls for efficient test pattern generation and test set compaction tools. Such tools were implemented using a genetic algorithm which maximises the number of potential faults covered by every test pattern. Experimental results for decision diagrams with up to 1763 inputs and 5329 nodes are presented. The efficiency of the genetic algorithm in this application is estimated.