Low-Voltage and High-Speed CMOS Circuit Design with Low-Power Mode

被引：0
|
作者：
Berg, Yngvar [1 ]
Mirmotahari, Omid [2 ]
机构：
[1] Buskerud & Vestfold Univ Coll, Dept Micro & Nanosyst Technol, Borre, Norway
[2] Univ Oslo, Dept Informat, Nanoelect Syst Grp, N-0316 Oslo, Norway
来源：
2015 IEEE CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS) | 2015年
关键词：
CMOS; Low-Voltage; High-Speed; Sleep Mode; Domino logic;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper we present a modified ultra-low-voltage and high-speed domino logic style with sleep mode for low-power and low-energy applications. The performance compared to conventional clock voltage switch logic is 15 times higher in terms of speed for a supply voltage equal to 300mV The low-power sleep mode consumes less than 1% of the power in high-performance mode. The CMOS process used for the simulated data presented is 90nm TSMC.
引用
收藏
页码：57 / 60
页数：4
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