A combinatorial architecture for instruction-level parallelism

The work presents a new principle for microprocessor design based on a pairwise-balanced combinatorial arrangement of processing and memory elements. The proposed apparatus uses two operand instructions so that a set of executable machine instructions is partitioned by these address pairs. This partitioning allows concurrent processing of data-independent instructions. Because the partitioning is done at compile-time, this design extracts substantial instruction-level parallelism from executable code without the overhead of run-time methods. The sequential consistency of the concurrent execution of instructions, including indirect addressing and conditional jumps, is ensured by inserted directives and queues regulation. Generation of executable code requires minor adjustments to a standard compiler. The hardware is built of regular modular components. This design provides a straightforward division of labor among the different functional units. The suggested combinatorial architecture offers a family of constructions with various degrees of performance enhancement. (C) 1998 Elsevier Science B.V.