共 50 条
- [2] Parallel computer architecture and instruction-level parallelism [J]. EURO-PAR 2002 PARALLEL PROCESSING, PROCEEDINGS, 2002, 2400 : 457 - 457
- [3] Reconfigurable instruction-level parallel processor architecture [J]. ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, 2003, 2823 : 208 - 220
- [4] An asynchronous superscalar architecture for exploiting instruction-level parallelism [J]. SEVENTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 2001, : 140 - 151
- [5] Scalable instruction-level parallelism [J]. COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, 2004, 3133 : 383 - 392
- [8] A dedicated image processor exploiting both spatial and instruction-level parallelism [J]. CAMP'97 - FOURTH IEEE INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURE FOR MACHINE PERCEPTION, PROCEEDINGS, 1997, : 106 - 115
- [9] Increasing instruction-level parallelism with instruction precomputation [J]. EURO-PAR 2002 PARALLEL PROCESSING, PROCEEDINGS, 2002, 2400 : 481 - 485
- [10] Limits of Instruction-Level Parallelism Capture [J]. 2013 INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE, 2013, 18 : 1664 - 1673