HARDWARE REDUCTION FOR LUT-BASED MEALY FSMs

被引：27

作者：

Barkalov, Alexander ^{[1
]}

Titarenko, Larysa ^{[1
]}

Mielcarek, Kamil ^{[1
]}

机构：

[1] Univ Zielona Gora, Inst Metrol Elect & Comp Sci, Ul Prof Z Szafrana 2, PL-65516 Zielona Gora, Poland

来源：

INTERNATIONAL JOURNAL OF APPLIED MATHEMATICS AND COMPUTER SCIENCE | 2018年 / 28卷 / 03期

关键词：

Mealy FSM; synthesis; FPGA; LUT; partition; encoding collections of output variables; IMPLEMENTATION;

D O I：

10.2478/amcs-2018-0046

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

引用

页码：595 / 607

页数：13

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