共 50 条
- [1] Optimizing Test Wrapper for Embedded Cores using TSV based 3D SOCs 2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, : 31 - 36
- [2] Optimization of Test Wrapper for TSV Based 3D SOCs JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2016, 32 (05): : 511 - 529
- [3] Optimization of Test Wrapper for TSV Based 3D SOCs Journal of Electronic Testing, 2016, 32 : 511 - 529
- [4] TSV-Aware 3D Test Wrapper Chain Optimization 2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2018,
- [5] Designing of IP Cores' Test Wrapper Based on BFD Algorithm INTERNATIONAL CONFERENCE ON MECHANISM SCIENCE AND CONTROL ENGINEERING (MSCE 2014), 2014, : 639 - 643
- [6] IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 1039 - 1039
- [7] Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs Journal of Electronic Testing, 2020, 36 : 239 - 253
- [8] Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2020, 36 (02): : 239 - 253
- [9] Using domain partitioning in wrapper design for IP cores under power constraints 25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2007, : 369 - +
- [10] Test Cost Optimization Technique for the Pre-Bond Test of 3D ICs 2012 IEEE 30TH VLSI TEST SYMPOSIUM (VTS), 2012, : 102 - 107