TEST WRAPPER OPTIMIZATION TECHNIQUE USING BDF AND GA FOR 3D IP CORES

被引:0
|
作者
Liu, Jun [1 ,2 ]
Qian, Qingqing [1 ,2 ]
Wu, Xi [1 ,2 ]
Ren, Fuji [3 ]
Wang, Wei [1 ,2 ]
Chen, Tian [1 ,2 ]
机构
[1] Hefei Univ Technol, Sch Comp & Informat, Hefei 230009, Peoples R China
[2] Hefei Univ Technol, AnHui Prov Key Lab Affect Comp & Adv Intelligent, Hefei 230009, Peoples R China
[3] Univ Tokushima, Fac Engn, Dept Informat Sci & Intelligent Syst, Tokushima 7708502, Japan
关键词
three dimensional intellectual property cores; wrapper chains; through silicon vias; test time; hardware overhead; DESIGN;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To reduce pre-bond and post-bond test cost for 3D IP (Three Dimensional Intellectual Property) cores, this paper proposed a test wrapper optimization technique using BFD(Best Fit Decreasing) and GA (Genetic Algorithm) algorithm under the constraints of TSVs(Through Silicon Vias) number, the proposed technique firstly used BFD to balance the length of pre-bond wrapper chains to reduce pre-bond test time. Then, on the basis of optimization results of pre-bond wrapper chains, the GA was used to stitch pre-bond wrapper chains to form balanced post-bond wrapper chains under the constrained TSVs number to reduce hardware overhead and post-bond test time. Experimental results demonstrated the presented methodology can effectively reduce hardware overhead at the cost of little increased test time.
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页数:6
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