An FPGA Based Compression Accelerator for Forex Trading System

被引：3

作者：

Jang, Ji Hoon ^{[1
]}

Lee, Seong Mo ^{[1
]}

Gwon, Oh Seong ^{[1
]}

Lee, Seung Eun ^{[1
]}

机构：

[1] Seoul Natl Univ Sci & Technol, Dept Elect Engn, 232 Gongneung Gil, Seoul 139743, South Korea

来源：

INFORMATION TECHNOLOGY: NEW GENERATIONS | 2016年 / 448卷

关键词：

FPGA; Hardware accelerator; Compression; Forex trading;

D O I：

10.1007/978-3-319-32467-8_62

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, we propose an FPGA based hardware accelerator for forex trading system. In the forex trading market, the trading volume of currencies is growing larger every year. In order to provide a real-time processing of large volume and high availability service, we focused on the two types of workload, where a bottleneck occurs. The bottleneck between an application server and an internal hard disk is caused by the overhead from storing the transaction logs, due to the bandwidth limitation of a hard disk. Our key idea is to suppress the overhead of transaction logging through the high throughput hardware compression. Compared to software compression, our hardware accelerator scored 6x better performance in compression throughput.

引用

页码：711 / 720

页数：10

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