On the punchthrough phenomenon in submicron MOS transistors

被引:10
|
作者
Fu, KY [1 ]
Tsang, YL [1 ]
机构
[1] MOTOROLA INC,ADV PROD RES & DEV LAB,AUSTIN,TX 78721
关键词
D O I
10.1109/16.568048
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
s the channel length of MOS transistors reduces to the submicron dimension, the punchthrough becomes more of a surface-initiated and gate-controlled phenomenon, A surface diffusion current (I-sdif) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending (Delta phi(so)). The DIBL effect increases rapidly with decreasing channel length, In addition, the extracted Delta phi(so) from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long submicron devices (approximate to 0.62 mu m) to the strong-inversion mode for deep submicron devices (approximate to 0.12 mu m). In general, I-sdif dominates over the low drain bias range and eventually converts to the bulk space-charge-limited current (I-scl) as the drain bias increases and the source/drain depletion regions connect, The drain bias for this conversion to occur strongly depends on the channel dimension, Only intermediate submicron devices (approximate to 0.37 mu m) in this study clearly show both the surface and bulk (space-charge-limited) punchthrough components, For long submicron devices, I-sdif essentially dominates, while for deep submicron devices, it converts rapidly to I-scl over the drain bias range investigated, A semi-empirical closed form equation is proposed to describe both I-sdif and I-scl and their merging over the entire range of drain bias, The punchthrough current simulated from this equation shows an excellent agreement with the experimental data.
引用
收藏
页码:847 / 855
页数:9
相关论文
共 50 条
  • [1] On the punchthrough phenomenon in submicron MOS transistors
    Motorola, Inc, Austin, United States
    IEEE Trans Electron Devices, 5 (847-855):
  • [2] The punchthrough phenomena in submicron polysilicon thin-film transistors
    Yaung, DN
    Fang, YK
    Huang, KC
    Wang, YJ
    Hung, CC
    Liang, MS
    Wuu, SG
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2000, 15 (02) : 225 - 228
  • [3] Mismatch characterization of submicron MOS transistors
    Bastos, J
    Steyaert, M
    Pergoot, A
    Sansen, W
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1997, 12 (02) : 95 - 106
  • [4] Characterizing the mismatch of submicron MOS transistors
    Lovett, SJ
    Clancy, R
    Welten, M
    Mathewson, A
    Mason, B
    ICMTS 1996 - 1996 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, PROCEEDINGS, 1996, : 39 - 42
  • [5] Mismatch Characterization of Submicron MOS Transistors
    J. Bastos
    M. Steyaert
    A. Pergoot
    W. Sansen
    Analog Integrated Circuits and Signal Processing, 1997, 12 : 95 - 106
  • [6] Punchthrough currents in sub-micron short channel MOS transistors
    Fu, KY
    Tsang, YL
    SOLID-STATE ELECTRONICS, 1997, 41 (03) : 435 - 439
  • [7] Submicron BiCMOS compatible high voltage MOS transistors
    Li, Yong Q.
    Salama, C.A.T.
    IEEE International Symposium on Power Semiconductor Devices & ICs, 1994, : 355 - 358
  • [8] RELIABILITY PROBLEMS OF SUBMICRON MOS-TRANSISTORS AND CIRCUITS
    KRAUTSCHNEIDER, WH
    TERLETZKI, H
    WANG, Q
    MICROELECTRONICS RELIABILITY, 1992, 32 (11) : 1499 - 1508
  • [9] A unified environment for the modeling of ultra deep submicron MOS transistors
    Gneiting, T
    NANOTECH 2003, VOL 2, 2003, : 368 - 371
  • [10] PUNCH-THROUGH PHENOMENON IN MOS TRANSISTORS.
    Owczarek, Artur K.
    Electron Technology (Warsaw), 1980, 13 (1-2): : 55 - 65