A 1.2 GFLOPS neural network chip for high-speed neural network servers

被引:4
|
作者
Kondo, Y
Koshiba, Y
Arima, Y
Murasaki, M
Yamada, T
Amishiro, H
Mori, H
Kyuma, K
机构
[1] MITSUBISHI ELECTR CORP,SYST LSI LAB,ITAMI,HYOGO 664,JAPAN
[2] MITSUBISHI ELECTR CORP,ULSI LAB,ITAMI,HYOGO 664,JAPAN
关键词
D O I
10.1109/4.509875
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes a digital neural network chip for high-speed neural network servers. The chip employs single-instruction multiple-data stream (SIMD) architecture consisting of 12 floating-point processing units, a control unit, and a nonlinear function unit. At a 50 MHz clock frequency, the chip achieves a peak speed performance of 1.2 GFLOPS using 24-bit floating-point representation, Two schemes of expanding the network size enable neural tasks requiring over 1 million synapses to be executed, The average speed performances of typical neural network models are also discussed.
引用
收藏
页码:860 / 864
页数:5
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