A Capacitor-less LDO with High PSR over a wide frequency range

This paper presents a capacitor-less low dropout (LDO) voltage PMOS regulator with high power supply rejection (PSR). The proposed LDO combines into a single core two differential stages: a primary one - as error amplifier for the negative feedback loop - and a secondary one, used to create a feedforward cancellation path from the supply to the gate of the pass transistor. With this arrangement the LDO can provide a PSR of -43dB at 1MHz for the maximum load current of 50mA. This performance is achieved with only 20 mu A quiescent current and a load capacitor of 100pF. The LDO is designed in a 0.18 mu m standard CMOS process.