Bottom-up digital system-level reliability modeling

被引：0

作者：

Amador, N. Ruiz ^{[1
,2
]}

Huard, V. ^{[1
]}

Pion, E. ^{[1
]}

Cacho, F. ^{[1
]}

Croain, D. ^{[1
]}

Robert, V. ^{[1
]}

Engels, S. ^{[1
]}

Flatresse, P. ^{[1
]}

Anghel, L. ^{[2
]}

机构：

[1] STMicroelect, Technol R&D, Crolles, France

[2] TIMA Lab, Grenoble, France

来源：

2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.

引用

页数：4

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