Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-μm CMOS

被引：35
|
作者：
Henrickson, L [1 ]
Shen, D
Nellore, U
Ellis, A
Oh, J
Wang, H
Capriglione, G
Atesoglu, A
Yang, A
Wu, P
Quadri, S
Crosbie, D
机构：
[1] Agere Syst, Santa Clara, CA 95054 USA
[2] IRF Semicond, Cupertino, CA 95014 USA
[3] Marvell Semicond, Sunnyvale, CA 94089 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 10期
关键词：
broad-band communication; CMOS integrated circuits; optical communication; phase-locked loops; SONET;
D O I：
10.1109/JSSC.2003.817586
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Here, we present a low-power fully integrated 10-Gb/s transceiver in 0.13-mum CMOS. This transceiver comprises full transmit and receive functions, including 1 : 16 multiplex and demultiplex functions, high-sensitivity limiting amplifier, on-chip 10-GHz clock synthesizer, clock-data recovery, 10-GHz data and clock drivers, and an SFI-4 compliant 16-bit LVDS interface. The transceiver exceeds all SONET/SDH (OC-192/STM-64) jitter requirements with significant margin: receiver high-frequency jitter tolerance exceeds 0.3 UIpp and transmitter jitter generation is 30 mUI(pp), All functionality and specifications (core and I/O), are achieved with power dissipation of less than 1 W.
引用
收藏
页码：1595 / 1601
页数：7
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