Design of a Conditional Sum Adder Based on Multiple-Valued Logic

被引：0

作者：

Wu Haixia ^{[1
]}

Zhong Shunan ^{[1
]}

Qu Xiaonan ^{[1
]}

Xia Qianbin ^{[1
]}

Cheng Yueyang ^{[1
]}

机构：

[1] Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China

来源：

2011 INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND CONTROL (ICECC) | 2011年

关键词：

Multiple-valued logic; Multiple-valued current-mode; Conditional sum addition;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In order to improve the performance of arithmetic VLSI system, a kind of multiple-valued current-mode (MVCM) circuitry based on dynamic source-coupled logic is presented. Using the circuitry, a 4-quatrit quaternary adder based on conditional sum algorithm is proposed, which implements 8-bit addition operation. The use of conditional sum logic improves the speed of calculating. The design is evaluated by HSPICE simulation in 0.18 mu m CMOS technology with the supply voltage of 1.8V, and the simulation shows that its power dissipation is 2.8mW, the delay of sum is 0.689ns, and the transistor counts is 636. The combination of MVCM circuits and relevant algorithms seems to be a solution for high performance arithmetic and logic units in VLSI system.

引用

页码：810 / 813

页数：4

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