Implementation of Dynamic Voltage and Frequency Scaling for System Level Power Reduction

被引:0
|
作者
Bhat, Shankaranarayana M. [1 ]
Srigowri [1 ]
Rao, Vinutha V. [1 ]
Pai, Vivekananda B. P. [1 ]
机构
[1] Manipal Univ, Manipal Inst Technol, Dept Elect & Commun Engn, Manipal, Karnataka, India
关键词
DVFS; low power; VLSI; CMOS; workload; system-level power;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
As the portability of electronic systems requires longer battery life, it is necessary that they must have mechanisms in place to reduce the power consumption. One of the techniques used to increase power efficiency at the system level is Dynamic Voltage and Frequency Scaling (DVFS). Variable workload provides an opportunity to scale the voltage and frequency dynamically, so that the power dissipation can be significantly reduced without appreciable impact on the throughput. The input data rate is taken as one of the indicators of the workload that the system has to handle. Higher workload as indicated by faster data-rate necessitates application of higher voltage and frequency to the system. On the other hand, a low data rate at the input, allows for computation at low voltage and low frequencies. The data-rate is estimated using a workload predictor and appropriate signals are generated to indicate the voltage and frequency to be selected. The scaled voltage and frequency were applied to the test circuits and the power dissipation is measured. The results demonstrate the correlation of the scaling of voltage and frequency with the input data rate and effect reduction of power dissipation.
引用
收藏
页码:425 / 430
页数:6
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