Design of a distributed shared memory for switch fabric and its FPGA implementation

Switch Fabrics are one of the main elements of data networks. They can be classified into several types based on their switching techniques. One of the most successful types is shared memory. A shared memory switch fabric works essentially as an output buffered switch, and therefore achieves the optimal throughput and delay performance. However memory bandwidth is a bottleneck in this architecture. In this paper, we have proposed a solution to resolve this problem. In our design, incoming cells are distributed among different memory banks instead of a monolithic centralized one. At the first step, incoming cells are being synchronized with internal cell time slot. Then during a time slot, words of all cells are distributed in different banks, so that every first words goes to the first bank, every second words goes to the second one and so on. In this scheme number of words in each cell must be equal to the number of memory banks. In the other side a similar mechanism reads words of stored cells, and makes outgoing cells. Address of Empty locations in memory and output queues are managed by another unit beside shared memory, called "pointer path". We have implemented our design on a VirtexII 8000 FPGA chip from Xilinx. Our design works in two modes, in a single chip mode the total capacity of the switch is 20 Gbps and 40 Gbps when two works in parallel.