FPGA Implementation of Memory Design and Testing

被引：0
|
作者：
Kumari, K. L. V. Ramana [1 ]
Rani, M. Asha [2 ]
Balaji, N. [3 ]
机构：
[1] VNRVJIET, Dept ECE, Hyderabad, Andhra Pradesh, India
[2] JNTUH, Dept ECE, Hyderabad, Andhra Pradesh, India
[3] JNTUK, Dept ECE, Narasaraopet, India
来源：
2017 7TH IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC) | 2017年
关键词：
Memory; BIST; Counter; Test data;
D O I：
10.1109/IACC.2017.110
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Memories are the most universal components of our day to day real time applications. Almost all application system chips contain some type of embedded memory chips, such as ROM, Static RAM, Dynamic RAM, and flash memory. The goal of the semiconductor technology is to continue to scale the technology in overall performance. Memories have complex design structures than any other core in SoC. Due to higher levels of integration and huge memory size, manufacturing cost of the device is reducing and testing cost is increasing. Testing is required to guarantee fault free products. Exhaustive number of bit patterns will take more time to test the circuit. Test algorithms are necessary to optimize the testing time. In this paper memory is designed and tested for different fault models. We have simulated and analyzed the memory design using ChipScope Pro and synthesis is done by using Spartan 3E FPGA.
引用
收藏
页码：552 / 555
页数：4
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