An FPGA based memory efficient shared buffer implementation

被引：2

作者：

Burns, Dwayne ^{[1
]}

Toal, Ciaran ^{[1
]}

McLaughlin, Kieran ^{[1
]}

Sezer, Sakir ^{[1
]}

Hutton, Mike ^{[2
]}

Cackovic, Kevin ^{[2
]}

机构：

[1] Queens Univ Belfast, Inst Elect Commun & Informat Technol, Belfast BT7 1NN, Antrim, North Ireland

[2] Altera Corp, San Jose, CA 95134 USA

来源：

2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/FPL.2007.4380740

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8Gbps and is scalable up to 20Gbps.

引用

页码：661 / 664

页数：4

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