An on-chip noise canceller with high voltage supply lines for nanosecond-range power supply noise

被引：3
|
作者：
Nakamura, Yasumi [1 ]
Takamiya, Makoto [1 ]
Sakurai, Takayasu [1 ]
机构：
[1] Univ Tokyo, Ctr Collaborat Res, Tokyo, Japan
来源：
2007 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2007年
关键词：
D O I：
10.1109/VLSIC.2007.4342683
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The canceller fabricated with 90-nm CMOS achieves 68% noise reduction with 2.0% power increase. Under the same noise reduction conditions, the area penalty for the canceller is 1/77 and 1/45 of those for the additional on-chip decoupling capacitors and the power supply lines respectively.
引用
收藏
页码：124 / 125
页数：2
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