High-performance dual-gate carbon nanotube FETs with 40-nm gate length

被引：98
|
作者：
Lin, YM [1 ]
Appenzeller, J
Chen, ZH
Chen, ZG
Cheng, HM
Avouris, P
机构：
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
[2] Inst Met Sci & Technol, Shenyang Natl Lab Mat Sci, Shenyang 110016, Peoples R China
来源：
IEEE ELECTRON DEVICE LETTERS | 2005年 / 26卷 / 11期
关键词：
carbon nanotube (CN); dual gate; field-effect transistor (FET); short-channel effect;
D O I：
10.1109/LED.2005.857704
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We report on a high-performance back-gated carbon nanotube field-effect transistor (CNFET) with a peak transconductance of 12.5 mu S and a delay time per unit length of tau/L = 19 ps/mu m. In order to minimize the parasitic capacitances and optimize the performance of scaled CNFETs, we have utilized a dual-gate design and have fabricated a 40-nm-gate CNFET possessing excellent subthreshold and output characteristics without exhibiting short-channel effects.
引用
收藏
页码：823 / 825
页数：3
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