A novel macromodel for power estimation in CMOS structures

We present in this paper a novel alternative for the internal power-dissipation estimation of CMOS structures. A first order macromodeling is developed, considering full submicronic additional effects such as input slew dependency of short-circuit currents and input-to-output coupling. We introduce a novel equivalent capacitance concept allowing a direct and frequency-independent comparison of the different power components. A direct link between fanout and input/output slew is studied in order to derive design-oriented analytical macromodels for the internal power components. Validations are presented by comparing simulated values (HSPICE level 6 foundry model 0.65 mu m) of power components to calculated values over a wide range of inverter configurations and control conditions. Discussion is given on a first-order generalization of this macromodel to gates. Evidence is given in terms of fanout and equivalent capacitance ratio of the controlling slope contribution on the internal power-dissipation components.