Design of Matrix-diagonal Allocator for Efficient Network-on-Chip Routers

被引：0

作者：

Wang, Gang ^{[1
]}

Wang, Qing ^{[1
]}

Li, Bing ^{[1
]}

Jiang, Wei ^{[1
]}

Xu, Yin ^{[1
]}

机构：

[1] Southeast Univ, Sch Integrated Circuits, Coll Instrument Sci & Engn, Nanjing, Jiangsu, Peoples R China

来源：

2017 INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2017年

关键词：

Network-on-Chip; router; matrix-diagonal allocator; virtual channel; switch; ARCHITECTURE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The performance of router directly impacts the Network-on-Chip (NoC) performance. This paper focus on developing efficient microarchitecture of allocator in the router and proposed matrix-diagonal allocator with high matching quality and low packets latency. The allocator, taking advantage of the fact that each element in the diagonal doesn't share the same row or column, includes matrix-diagonal virtual channel (VC) allocator and matrix-diagonal switch channel. Experimental results show that our design cannot only decrease packets latency, but also improve throughput.

引用

页数：2

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