A Performance Model for Network-on-Chip Wormhole Routers

被引：4
|
作者：
Zhang, Youhui [1 ]
Dong, Xiaoguo [2 ]
Gan, Siqing [2 ]
Zheng, Weimin [1 ]
机构：
[1] Tsinghua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China
[2] Cent S Univ, Dept Math Sci & Comp Technol, Changsha 410075, Hunan, Peoples R China
来源：
JOURNAL OF COMPUTERS | 2012年 / 7卷 / 01期
基金：
美国国家科学基金会;
关键词：
Network-on-Chip; Markov chain; queuing theory; performance analysis;
D O I：
10.4304/jcp.7.1.76-84
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
A generic analytical performance model of single-channel wormhole routers is presented using the M/D/1/B queuing theory. Compared with previous work, the flow-control feedback mechanism is studied in detail, and a computing method bases on Markov chain for the flow-control feedback probability is proposed. Compared with BookSim, a well-known cycle-accurate Network-on-Chip (NoC) simulator, this model presents accurate results on key metrics: the average relative error of flow-control feedback probability is about 7.87%. In addition, based on the model of single-channel routers, the asymmetric multi-channel and symmetric multi-channel structured routers are both modeled respectively.
引用
收藏
页码：76 / 84
页数：9
相关论文
共 50 条
  • [1] Model of Network-on-Chip routers and performance analysis
    Zhang, Youhui
    Dong, Xiaoguo
    Gan, Siqing
    Zheng, Weimin
    [J]. IEICE ELECTRONICS EXPRESS, 2011, 8 (13): : 986 - 993
  • [2] Allocator Implementations for Network-on-Chip Routers
    Becker, Daniel U.
    Dally, William J.
    [J]. PROCEEDINGS OF THE CONFERENCE ON HIGH PERFORMANCE COMPUTING NETWORKING, STORAGE AND ANALYSIS, 2009,
  • [3] ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers
    Seitanidis, I.
    Psarras, A.
    Dimitrakopoulos, G.
    Nicopoulos, C.
    [J]. 2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE), 2014,
  • [4] Interfacing cores and routers in Network-on-Chip using GALS
    Kundu, Santanu
    Chattopadhyay, Santanu
    [J]. 2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, : 154 - 157
  • [5] A power and performance model for network-on-chip architectures
    Banerjee, N
    Vellanki, P
    Chatha, KS
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1250 - 1255
  • [6] Probabilistic Analysis of Power-Gating in Network-on-Chip Routers
    Nasirian, Nasim
    Soosahabi, Reza
    Bayoumi, Magdy A.
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019, 66 (02) : 242 - 246
  • [7] Routing Aware and Runtime Detection for Infected Network-on-Chip Routers
    Daoud, Luka
    Rafla, Nader
    [J]. 2018 IEEE 61ST INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2018, : 775 - 778
  • [8] SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers
    Konstantinou, Dimitrios
    Nicopoulos, Chrysostomos
    Lee, Junghee
    Sirakoulis, Georgios Ch
    Dimitrakopoulos, Giorgos
    [J]. 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
  • [9] ViChaR: A dynamic virtual channel regulator for network-on-chip routers
    Nicopoulos, Chrysostomos A.
    Park, Dongkook
    Kim, Jongman
    Vijaykrishnan, N.
    Yousif, Mazin S.
    Das, Chita R.
    [J]. MICRO-39: PROCEEDINGS OF THE 39TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2006, : 333 - +
  • [10] An Analytical Model for Hypercube Network-On-Chip Systems with Wormhole Switching and Fully Adaptive Routing
    Liu, Jin
    Wang, Xiaofeng
    Ren, Hongmin
    Wang, Jin
    Kim, Jeong-Uk
    [J]. INTERNATIONAL JOURNAL OF GRID AND DISTRIBUTED COMPUTING, 2012, 5 (04): : 33 - 42
12345