Mapping a pipelined data path onto a network-on-chip

被引:1
|
作者
Kubisch, Stephan [1 ]
Cornelius, Claas [1 ]
Hecht, Ronald [1 ]
Timmermarm, Dirk [1 ]
机构
[1] Univ Rostock, Inst Appl Microelect & Comp Engn, D-18051 Rostock, Germany
关键词
network-on-chip; system-on-chip; quality-of-service; application-specific; FPGA;
D O I
10.1109/SIES.2007.4297333
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
During the last years, Networks-on-Chip (NoCs) have become a true alternative for the design of complex integrated Systems-on-Chip (SoC). Much effort has been spent for research on functionalities, mechanisms, and Quality-of-Service (QoS) features in NoCs. Hence, a broad and multi-faceted design space exists but leaves open, which mechanisms and design paradigms actually tip the scales for the chosen application domain. In this paper, we discuss the level of QoS needed in a specific NoC for a packet processing application. This is done in the light of preliminary investigations for the redesign of an existing packet processing system because that system's current architecture exhibits drawbacks regarding performance and further scalability. Therefore, we considered to take advantage of an NoC communication architecture. A simple NoC was developed, which knowingly omits sophisticated QoS mechanisms. Relying on the lessons, which have learned from the history and development of the Internet, we argue that a simple and plain NoC suffices for applications as the one discussed.
引用
收藏
页码:178 / 185
页数:8
相关论文
共 50 条
  • [1] A Locally Reconfigurable Network-on-Chip Architecture and Application Mapping onto it
    Soumya, J.
    Sharma, Ashish
    Chattopadhyay, Santanu
    [J]. 18TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST, 2014,
  • [2] Optimized Mapping Spiking Neural Networks onto Network-on-Chip
    Ji, Yu
    Zhang, Youhui
    Liu, He
    Zheng, Weimin
    [J]. ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, ICA3PP 2016, 2016, 10048 : 38 - 52
  • [3] A Reliability Aware Application Mapping onto Mesh based Network-on-Chip
    Chatterjee, Navonil
    Reddy, Sheshivardhan
    Reddy, Shilpa
    Chattopadhyay, Santanu
    [J]. 2016 3RD INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN INFORMATION TECHNOLOGY (RAIT), 2016, : 537 - 542
  • [4] A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip
    Sahu, Pradip Kumar
    Manna, Kanchan
    Shah, Tapan
    Chattopadhyay, Santanu
    [J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2015, 24 (08)
  • [5] Reliability-aware application mapping onto mesh based Network-on-Chip
    Chatterjee, Navonil
    Mukherjee, Priyajit
    Chattopadhyay, Santanu
    [J]. INTEGRATION-THE VLSI JOURNAL, 2018, 62 : 92 - 113
  • [6] A Constructive Heuristic for Application Mapping onto an Express Channel based Network-on-Chip
    D'souza, Sandeep
    Soumya, J.
    Chattopadhyay, Santanu
    [J]. 2015 19TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2015,
  • [7] Testing aware dynamic mapping for path-centric network-on-chip test
    Jiang, Shuyan
    Wu, Qiong
    Chen, Shuyu
    Zhan, Junkai
    Wang, Junshi
    Ebrahimi, Masoumeh
    Huang, Letian
    [J]. INTEGRATION-THE VLSI JOURNAL, 2019, 67 : 134 - 143
  • [8] Application Mapping onto Mesh Structured Network-on-Chip using Particle Swarm Optimization
    Sahu, Pradip Kumar
    Venkatesh, Putta
    Gollapalli, Sunilraju
    Chattopadhyay, Santanu
    [J]. 2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, : 335 - 336
  • [9] Revive Path: Resilient Network-on-Chip Design Through Data Path Salvaging of Router
    Han, Yin-He
    Liu, Cheng
    Lu, Hang
    Li, Wen-Bo
    Zhang, Lei
    Li, Xiao-Wei
    [J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2013, 28 (06) : 1045 - 1053
  • [10] RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh Network-on-Chip
    Choudhary, Jitesh
    Soumya, J.
    Cenkeramaddi, Linga Reddy
    [J]. 2021 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM-LEVEL INTERCONNECT PATHFINDING (SLIP 2021), 2021, : 52 - 58