Unspecified transition faults: A transition fault model for at-speed fault simulation and test generation

A transition fault model is described, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. At-speed test application allows a circuit to be tested under its normal-operation conditions. However, fault simulation and test generation for standard transition faults become significantly more complex due to the need to handle faulty signal transitions that span multiple clock cycles. As a result, each transition fault needs to be considered multiple times, with multiple sizes of the extra delay on the faulty line. The proposed fault model alleviates this shortcoming by introducing unspecified values into the faulty circuit when fault effects may occur, thus allowing faults of all possible sizes to be encompassed in a single fault. Fault detection potentially occurs when an unspecified value reaches a primary output. "Pessimistic," "optimistic," and "random" versions of the fault model and corresponding fault coverages are defined. If a single fault coverage is to The computed, the pessimistic one provides the lowest fault coverage. By using the optimistic or random version, it is possible to obtain a range of possible fault coverages that is analogous to the range of sizes of transition faults. For certain applications, it is also possible to include more than one version of every fault in a single set of target faults and to compute a single fault coverage. Experimental results of fault simulation and test generation are presented to demonstrate the behavior of the model and to compare it with other fault models.