Realization of vertical P+ wall through-wafer

被引：2

作者：

Sanchez, JL ^{[1
]}

Scheid, E ^{[1
]}

Austin, P ^{[1
]}

Breil, M ^{[1
]}

Carrire, H ^{[1
]}

Dubreuil, P ^{[1
]}

Imbernon, E ^{[1
]}

Rossel, F ^{[1
]}

Rousset, B ^{[1
]}

机构：

[1] CNRS, LAAS, F-31077 Toulouse 4, France

来源：

MICROMACHINING AND MICROFABRICATION PROCESS TECHNOLOGY IX | 2004年 / 5342卷

关键词：

Deep RIE of silicon; P+ wall; bi-directional power devices; electrical via;

D O I：

10.1117/12.531533

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

P+ walls through wafer can be considered as key regions in the 3D architecture of new bi-directional current and voltage power integrated devices. Moreover, these P+ walls can be used as electrical vias in the design of microsystems, in order to make easier 3D packaging. In this paper, we demonstrate the possibility of fabricating these P+ walls combining the deep RIE of silicon and deposit of boron-doped polysilicon.

引用

页码：119 / 127

页数：9

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