A Low-Power, High-Speed CMOS/CML 16:1 Serializer

This paper presents a low power CMOS/CML 16:1 serializer for optical data transmission systems. The serializer comprises a 16:N CMOS multiplexer, a CMOS to CML data converter, a N:1 CML multiplexer, a CML to CMOS clock converter and clock dividers. The serializer was implemented in two technologies: fabricated in 65-nm CMOS process and a total area of 110 mu m x 390 mu m, consumes 106mW from 1/1.8V supplies, designed in 45-nm CMOS process and a total area of 140 mu m x 360 mu m, consumes 50mW from 0.9/1.2-V supplies. In both cases, simulated DDJ is less than 3ps under worst case conditions. Advantages of using static CMOS and CML topologies together for high-speed digital signals are discussed. A design method for avoiding timing issues is presented.