Thermal Modeling and Characterization of the Embedded Micro Wafer Level Package (EMWLP) at the Package- and System-Level

In this paper, package-level thermal modeling of the embedded micro-wafer-level-packaging (EMWLP) package has been performed to extract the parametric trends for thermal design guidelines of an eccentric single active die embedded alongside an integrated passive device (IPD), as shown in Fig.1 (with optional heat sink as a cooling solution). Exploratory thermal resistance modeling of an embedded two-die-stack has also been conducted. The effect of the mold compound used in the thermal models is further considered under the following parameters: mold thickness and thermal conductivity (0.4 W/mK to 2.5 W/mK). The effects of heat spreaders and heat sinks on the package thermal resistance are also studied, with due consideration paid to the above mold parameters. Furthermore, experimental characterization has been conducted to validate the package-level simulation for the single active die model, conforming to the JEDEC JESD 51-2A Thermal Measurements in Natural Convection standard. Finally, simulation results for a general system-level thermal modeling in both cellphone as well as laptop systems are also performed. Thermal management solutions for both scenarios, such as thermal vias and heat spreaders, are studied, with an optimal cooling solution proposed.