Power analysis resistant hardware implementations of AES

This paper presents the first FPGA implementation of the Advanced Encryption Standard (AES) with masking countermeasure for the power analysis (PA) attacks. PA is a powerful side-channel analysis (SCA) attack. A side-channel analysis (SCA) attack takes advantage of implementation specific characteristics to recover the secret parameters involved in the computation. The goals of side-channel attack countermeasures are reducing the correlation between the side-channel data and the secret data. Data masking is one of the most powerful countermeasure against side channel attacks. The message and the key are masked with some random values at the beginning of computations. We have implemented the AES algorithm on an FPGA by using two different masking method: multiplicative and additive.