Advanced gate process critical dimension control in semiconductor manufacturing

被引：5

作者：

Sasano, H ^{[1
]}

Liu, W ^{[1
]}

Mui, DSL ^{[1
]}

Yoo, K ^{[1
]}

Yamartino, J ^{[1
]}

机构：

[1] Appl Mat Inc, Sunnyvale, CA USA

来源：

2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/ISSM.2003.1243308

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Control on the order of nanometers is crucial for gate etch, in which the smaller the gate, the faster and more valuable the resulting chip. To date, feed-forward and closed-loop schemes have been created, using a series of standalone systems in the process flow. Lately, integrating metrology capabilities with an etch platform has been proven practicable. This paper presents a model for closed-loop control of the gate etch process and demonstrates the virtual elimination of post-etch critical dimension variation that results.

引用

页码：382 / 385

页数：4

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