FPGA implementation of median filter

被引：13

作者：

Maheshwari, R

Rao, SSSP

Poonacha, PG

机构：

来源：

TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年

关键词：

D O I：

10.1109/ICVD.1997.568194

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper gives the algorithm and implementation details of a sliding real time 3 x 3 median filter. The design is implemented on a Xilinx XC4010 FPGA chip. It is tested and integrated at ER&DC1, Trivandrum. The design is tailored to exploit certain features of sliding windows. The Algorithm used to implement median filter is very efficient and implementation results show the significant improvements in operating frequency and hardware requirements over general purpose techniques.

引用

页码：523 / 524

页数：2

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