Operation-Aware Assist Circuit Design for Improved Write Performance of FinFET based SRAM

Aggressively scaled SRAM is highly vulnerable to short channel and process variation effects. FinFET technology emerges as a device level solution to overcome these scaling limitations while assist techniques aid super-scaled SRAM to achieve better performance and stability. In this paper, we propose two operation-aware assist circuits, namely, Split and Suppressed cell Supply (SSS) and Negative Bit-Line scheme incorporated SSS (SSS-NBL) to provide better write performance without compromising read performance. We exploit cell supply collapse scheme in SSS to achieve low power consumption and improved write performance whereas SSS-NBL further ameliorates write performance. A new analytical model is derived for SSS-NBL. Simulation results reflect an improvement of 0.53% in read performance of 6T SRAM cell whereas 34.02% and 27.86% in write performance using SSS for 6T and PPN-based 10T SRAM cell, respectively. Similarly, SSS-NBL offers 37% and 32.63% improved write performance over 6T and PPN-based 10T bit-cell, respectively.