Impedance Modeling and Stability Analysis of Grid-Connected DFIG-Based Wind Farm With a VSC-HVDC

被引:134
|
作者
Sun, Kun [1 ]
Yao, Wei [1 ]
Fang, Jiakun [2 ]
Ai, Xiaomeng [1 ]
Wen, Jinyu [1 ]
Cheng, Shijie [1 ]
机构
[1] Huazhong Univ Sci & Technol, Sch Elect & Elect Engn, State Key Lab Adv Electromagnet Engn & Technol, Wuhan 430074, Peoples R China
[2] Aalborg Univ, Dept Energy Technol, DK-9220 Aalborg, Denmark
基金
中国国家自然科学基金;
关键词
Doubly fed induction generators; Wind farms; Phase locked loops; Integrated circuit modeling; Impedance; Power conversion; Double-fed induction generator (DFIG); impedance-based method; phase-locked loop (PLL); subsynchronous oscillation (SSO); voltage source converter (VSC)-HVdc; wind farm; VOLTAGE; GENERATOR; SEQUENCE; SSR; DQ;
D O I
10.1109/JESTPE.2019.2901747
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new type of subsynchronous oscillation (SSO) has been observed recently in double-fed induction generator (DFIG)-based wind farm integrated via voltage source converter-based HVdc (VSC-HVdc) system. However, the mechanism of this emerging oscillation is not entirely understood. In this paper, the impedance models of DFIG with and without considering the phase-locked loop (PLL) dynamics are both derived. Then, the impedance-based simplified equivalent circuit of the multiple DFIGs interfaced with VSC-HVdc system is established. This model can be further represented as the <italic>RLC</italic> series resonance circuit to quantify the start-oscillating condition intuitively. The theoretical analysis results show that DFIGs behave as an inductance in series with a negative resistance at the resonance point, whose interaction with wind farm side VSC (WFVSC) (regard as a resistancex2013;capacitance) constitutes an equivalent <italic>RLC</italic> resonance circuit with negative resistance. Therefore, the oscillation tends to occur due to the negative damping. In addition, the impact of various factors including number of grid-connected DFIG-wind turbines (WTs), wind speed, and parameters of PI controllers and PLL on the SSO characteristics is analyzed based on the proposed simplified model. Finally, the correctness of the theoretical analysis is validated by both the time-domain simulation and hardware-in-loop experiments.
引用
收藏
页码:1375 / 1390
页数:16
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