200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator

被引：6

作者：

Weiss, Naftali ^{[1
,2
]}

Cooke, Gregory ^{[1
]}

Schvan, Peter ^{[2
]}

Chevalier, Pascal ^{[3
]}

Cathelin, Andreia ^{[3
]}

Voinigescu, Sorin P. ^{[1
]}

机构：

[1] Univ Toronto, ECE Dept, Toronto, ON, Canada

[2] Ciena Corp, Analog Design Dept, Ottawa, ON, Canada

[3] STMicroelectronics, Technol & Design Platforms Dept, Crolles, France

来源：

ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) | 2021年

关键词：

ADC front-end; SiGe BiCMOS; mm-wave; quadrature phase generation;

D O I：

10.1109/ESSCIRC53450.2021.9567791

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 55nm SiGe BiCMOS ADC front-end is reported with record 200-GS/s sampling rate and SNDR larger than 32 dB and 253 dB up to 45 GHz and 63 GHz, respectively. This performance is enabled by the architecture of the front-end with a single level of samplers which maximizes bandwidth and linearity, by the reduced-voltage MOS CML switch, and by a dc-to-62 GHz, 25% duty-cycle non-overlapping quadrature clock generator. The total power consumption of the ADC front-end is 635 mW.

引用

页码：483 / 486

页数：4

共 22 条

[1] Track and Hold Amplifier Investigation for 100-GHz Bandwidth, 200-GS/s ADC Front Ends
Cooke, Gregory
Weiss, Naftali
Schvan, Peter
Chevalier, Pascal
Cathelin, Andreia
Voinigescu, Sorin P.
IEEE SOLID-STATE CIRCUITS LETTERS, 2022, 5 : 54 - 57
[2] DC-62 GHz 4-Phase 25% Duty Cycle Quadrature Clock Generator
Weiss, Naftali
Shopov, Stefan
Schvan, Peter
Chevalier, Pascal
Cathelin, Andreia
Voinigescu, Sorin P.
2017 IEEE COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM (CSICS), 2017,
[3] RF Receiver Front-End Employing IIP2-Enhanced 25&x0025; Duty-Cycle Quadrature Passive Mixer for Advanced Cellular Applications
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IEEE ACCESS, 2020, 8 : 8166 - 8177
[4] Front-End Programmable 40 GS/s Monobit ADC in 45 nm SOI Technology
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Bonner-Stewart, Jeffrey F.
Turner, Steven Eugene
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2024, 72 (03) : 2031 - 2038
[5] An UWB 18.5 GS/s Sampling Front-End for a 74 GS/s 5-bit ADC in 22 nm FDSOI
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[6] Analysis and design of a high-linearity receiver RF front-end with an improved 25%-duty-cycle LO generator for WCDMA/GSM applications
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Li Weinan
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JOURNAL OF SEMICONDUCTORS, 2012, 33 (02)
[7] Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s
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Groezing, Markus
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (09) : 2599 - 2610
[8] Analysis and design of a high-linearity receiver RF front-end with an improved 25%-duty-cycle LO generator for WCDMA/GSM applications附视频
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[9] An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit
Jiang, Shan
Do, Manh Anh
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Lim, Wei Meng
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (06) : 1430 - 1440
[10] A 12-bit 2-GS/s Pipelined ADC Front-end Stage with Aperture Error Tuning and Split MDAC
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2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,

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