200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator

被引：6

作者：

Weiss, Naftali ^{[1
,2
]}

Cooke, Gregory ^{[1
]}

Schvan, Peter ^{[2
]}

Chevalier, Pascal ^{[3
]}

Cathelin, Andreia ^{[3
]}

Voinigescu, Sorin P. ^{[1
]}

机构：

[1] Univ Toronto, ECE Dept, Toronto, ON, Canada

[2] Ciena Corp, Analog Design Dept, Ottawa, ON, Canada

[3] STMicroelectronics, Technol & Design Platforms Dept, Crolles, France

来源：

ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) | 2021年

关键词：

ADC front-end; SiGe BiCMOS; mm-wave; quadrature phase generation;

D O I：

10.1109/ESSCIRC53450.2021.9567791

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 55nm SiGe BiCMOS ADC front-end is reported with record 200-GS/s sampling rate and SNDR larger than 32 dB and 253 dB up to 45 GHz and 63 GHz, respectively. This performance is enabled by the architecture of the front-end with a single level of samplers which maximizes bandwidth and linearity, by the reduced-voltage MOS CML switch, and by a dc-to-62 GHz, 25% duty-cycle non-overlapping quadrature clock generator. The total power consumption of the ADC front-end is 635 mW.

引用

页码：483 / 486

页数：4

共 22 条

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2025, 60 (01) : 244 - 259
[22] A 112-GS/s 1-to-4 ADC front-end with more than 35-dBc SFDR and 28-dB SNDR up to 43-GHz in 130-nm SiGe BiCMOS
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Groezing, M.
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Le, S. T.
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