Implementation of Multiple-Precision Floating-Point Arithmetic on Intel Xeon Phi Coprocessors

被引：1
|
作者：
Takahashi, Daisuke [1 ]
机构：
[1] Univ Tsukuba, Ctr Computat Sci, 1-1-1 Tennodai, Tsukuba, Ibaraki 3058573, Japan
来源：
COMPUTATIONAL SCIENCE AND ITS APPLICATIONS - ICCSA 2016, PT II | 2016年 / 9787卷
关键词：
ALGORITHM; DIVISION;
D O I：
10.1007/978-3-319-42108-7_5
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose an implementation of multiple-precision floating-point addition, subtraction, multiplication, division and square root on Intel Xeon Phi coprocessors. Using propagated carries in multiple-precision floating-point addition is a major obstacle to vectorization and parallelization. By using the carry skip method, the operation of performing propagated carries in the multiple-precision floating-point addition can be vectorized and parallelized. A parallel implementation of floating-point real FFT-based multiplication is presented, as multiplication is a fundamental operation in fast multiple-precision arithmetic. The experimental results of multiple-precision floating-point addition, multiplication, division and square root operations on an Intel Xeon Phi 5110P are then reported.
引用
收藏
页码：60 / 70
页数：11
相关论文
共 50 条
  • [1] ALGORITHM 693 - A FORTRAN PACKAGE FOR FLOATING-POINT MULTIPLE-PRECISION ARITHMETIC
    SMITH, DM
    [J]. ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE, 1991, 17 (02): : 273 - 283
  • [2] A Modular-Positional Computation Technique for Multiple-Precision Floating-Point Arithmetic
    Isupov, Konstantin
    Knyazkov, Vladimir
    [J]. PARALLEL COMPUTING TECHNOLOGIES (PACT 2015), 2015, 9251 : 47 - 61
  • [3] Lattice QCD on Intel® Xeon Phi™ Coprocessors
    Joo, Balint
    Kalamkar, Dhiraj D.
    Vaidyanathan, Karthikeyan
    Smelyanskiy, Mikhail
    Pamnany, Kiran
    Lee, Victor W.
    Dubey, Pradeep
    Watson, William, III
    [J]. SUPERCOMPUTING (ISC 2013), 2013, 7905 : 40 - 54
  • [4] Effective SIMD Vectorization for Intel Xeon Phi Coprocessors
    Tian, Xinmin
    Saito, Hideki
    Preis, Serguei V.
    Garcia, Eric N.
    Kozhukhov, Sergey S.
    Masten, Matt
    Cherkasov, Aleksei G.
    Panchenko, Nikolay
    [J]. SCIENTIFIC PROGRAMMING, 2015, 2015
  • [5] Multiple precision floating-point arithmetic on SIMD processors
    van der Hoeven, Joris
    [J]. 2017 IEEE 24TH SYMPOSIUM ON COMPUTER ARITHMETIC (ARITH), 2017, : 2 - 9
  • [6] Communication Models for Distributed Intel Xeon Phi Coprocessors
    Neuwirth, Sarah
    Frey, Dirk
    Bruening, Ulrich
    [J]. 2015 IEEE 21ST INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS), 2015, : 499 - 506
  • [7] A MULTIPLE-PRECISION FLOATING-POINT INTERPRETIVE PROGRAM FOR CONTROL DATA 1604
    STROUD, AH
    SECREST, D
    [J]. COMPUTER JOURNAL, 1963, 6 (01): : 62 - &
  • [8] (FLOATING-POINT DYNAMIC-VARIABLE-RANGE MULTIPLE-PRECISION OPERATORS)
    FRECON, L
    CLAIRE, L
    [J]. ELECTRONICS LETTERS, 1972, 8 (08) : 191 - &
  • [9] Exploring SIMD for Molecular Dynamics, Using Intel®Xeon®Processors and Intel®Xeon Phi™ Coprocessors
    Pennycook, S. J.
    Hughes, C. J.
    Smelyanskiy, M.
    Jarvis, S. A.
    [J]. IEEE 27TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS 2013), 2013, : 1085 - 1097
  • [10] MPFR: A multiple-precision binary floating-point library with correct rounding
    Fousse, Laurent
    Hanrot, Guillaume
    Leflvre, Vincent
    Plissier, Patrick
    Zimmermann, Paul
    [J]. ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE, 2007, 33 (02):
12345