ION BEAM IRRADIATION EFFECTS IN KINTEX-7 FPGA RESOURCES

A comprehensive set of measurements has been pursued by our group to detect and characterize Single Event Upsets (SEUs) at the level of configuration memory (CRAM) and other logic resources on the chip such as random-access memory (BRAM) or user-accessible Flip Flop registers (FFs). The device under study was a Xilinx Kintex-7 Field Programmable Gate Array (FPGA) build on TSMC's 28 nm technology node. Careful attention was given to the device behaviour when the integrity of its configuration memory was corrupted due to SEU occurrence. The device sensibility to its configuration corruption due to the SEU was further investigated employing SEM IP core as a primary mitigation solution for CRAM integrity. Both software and electrical parameters have been recorded with a custom-made radiation hardness qualification test bench. The SEU rates and cross-sections were determined based on data collected during test beam sessions using several ion species with different Linear Energy Transfer (LET).