Video Chain Demonstrator on Xilinx Kintex7 FPGA with EdkDSP Floating Point Accelerators

被引：0
|
作者：
Kadlec, Jiri [1 ]
机构：
[1] UTIA AV CR Vvi, Inst Informat Theory & Automat, Prague, Czech Republic
来源：
Proceedings International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS XV) | 2015年
关键词：
floating point accelerators; reconfigurability; video processing; programmable logic;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
this paper briefly describes basic Kintex7 FPGA video pipe infrastructure for UTIA demonstrator in the ARTEMIS JU project ALMARVI. The video pipeline is combined with the run-time reprogrammable vector floating point EdkDSP accelerators on the same FPGA chip.
引用
收藏
页码：310 / 314
页数：5
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