Area and power consumption efficient VLSI implementation of programmable comb decimation filter with low switching noise

Power consumption, switching noise and area are among the most important parameters of decimation filters used in Sigma-Delta A/D converters. We found that IIR-FIR implementation of a comb decimator gives the best compromise regarding this 3 parameters by using systematic method for switching noise and power consumption reduction and besides it is very easy to change the decimation factor. A programmable A/D converter has been built using noise optimized 2(nd) order modulator and optimized 3(rd) order comb decimator with f(ovs)=4MHz and programmable oversampling ratios M=256, 128, 64. The area needed using 0.6 mum CMOS technology is slightly less than 0.7 mm(2). Average current consumption is approx. 2 times smaller and switching noise injected into the substrate is reduced almost 5 times compared to standard implementation. Measured results suggest that because of very low switching noise it is possible to use such IP block in high-resolution mixed-signal ASICs.