Advertiser Elevator: A Fault Tolerant Routing Algorithm for Partially Connected 3D Network-on-Chips

被引:0
|
作者
Taheri, Ebadollah [1 ]
Isakov, Mihailo [1 ]
Patooghy, Ahmad [1 ]
Kinsy, Michel A. [1 ]
机构
[1] Boston Univ, ASCS Lab, Dept Elect & Comp Engn, Boston, MA 02215 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we propose an adaptive routing algorithm for vertically partially connected 3D NoCs to (1) overcome failures in vertical links, and (2) find the nearest available vertical link for rerouting of packets. To track the position of each vertical link and distance to the other nodes, the proposed routing algorithm, named Advertiser Elevator, indexes each vertical link and implements a mechanism for announcing and sharing these indexes with the other nodes of the network. Packets are routed toward the nearest vertical link based on received indexes. The routing algorithm tolerates vertical link failures by interpreting the absence of index messages from a vertical link node as a link failure at the node. Packets are rerouted around failed links based on collected messages. The performance of the Advertiser Elevator routing algorithm is evaluated using the Access Noxim NoC simulator under different network congestion levels and fault rates. The results show that the proposed routing algorithm (1) is able to deliver packets as long as there are at least four live vertical links in the network (e.g., corner links) and (2) improves the average network latency by 15% over the well-known Elevator-First routing algorithm.
引用
收藏
页码:136 / 139
页数:4
相关论文
共 50 条
  • [1] Logic-Based Implementation of Fault-Tolerant Routing in 3D Network-on-Chips
    Niazmand, Behrad
    Azad, Siavoosh Payandeh
    Flich, Jose
    Raik, Jaan
    Jervan, Gert
    Hollstein, Thomas
    2016 TENTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2016,
  • [2] A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips
    Jouybari, Hoda Naghibi
    Mohammadi, Karim
    MICROPROCESSORS AND MICROSYSTEMS, 2014, 38 (08) : 991 - 999
  • [3] Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant Network-on-Chips
    Man, Ka Lok
    Yedluri, Karthik
    Kapoor, Hemangee K.
    Lei, Chi-Un
    Lim, Eng Gee
    Ma, Jieming
    CEIS 2011, 2011, 15
  • [4] A Performance Enhanced Adaptive Routing Algorithm for 3D Network-on-Chips
    Zeng, Lian
    Pan, Tieyuan
    Jiang, Xin
    Watanabe, Takahiro
    TENCON 2015 - 2015 IEEE REGION 10 CONFERENCE, 2015,
  • [5] Q-Learning-based Routing Algorithm for 3D Network-on-Chips
    Bolucu, Nurettin
    Tosun, Suleyman
    2021 24TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2021, : 33 - 36
  • [6] An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-Chips
    Dai, Jindun
    Jiang, Xin
    Li, Renjie
    Watanabe, Takahiro
    2017 IEEE 11TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC 2017), 2017, : 29 - 36
  • [7] A Link Fault-Tolerant Routing Algorithm for Mesh-of-Tree based Network-on-Chips
    Pushparaj, Joshua
    Bhanu, P. Veda
    Soumya, J.
    2019 IEEE INTERNATIONAL SYMPOSIUM ON SMART ELECTRONIC SYSTEMS (ISES 2019), 2019, : 181 - 184
  • [8] HAFTA: Highly adaptive fault-tolerant routing algorithm for two-dimensional network-on-chips
    Ipek, Anil
    Tosun, Suleyman
    Ozdemir, Suat
    CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2021, 33 (21):
  • [9] Cool Elevator: A Thermal-Aware Routing Algorithm for Partially Connected 3D NoCs
    Taheri, Ebadollah
    Patooghy, Ahmad
    Mohammadi, Karim
    2016 6TH INTERNATIONAL CONFERENCE ON COMPUTER AND KNOWLEDGE ENGINEERING (ICCKE), 2016, : 111 - 116
  • [10] A deadlock-free routing algorithm for irregular 3D network-on-chips with wireless links
    Mohseni, Zeynab
    Reshadi, Midia
    JOURNAL OF SUPERCOMPUTING, 2018, 74 (02): : 953 - 969