共 50 条
- [1] Logic-Based Implementation of Fault-Tolerant Routing in 3D Network-on-Chips 2016 TENTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2016,
- [3] Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant Network-on-Chips CEIS 2011, 2011, 15
- [4] A Performance Enhanced Adaptive Routing Algorithm for 3D Network-on-Chips TENCON 2015 - 2015 IEEE REGION 10 CONFERENCE, 2015,
- [5] Q-Learning-based Routing Algorithm for 3D Network-on-Chips 2021 24TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2021, : 33 - 36
- [6] An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-Chips 2017 IEEE 11TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC 2017), 2017, : 29 - 36
- [7] A Link Fault-Tolerant Routing Algorithm for Mesh-of-Tree based Network-on-Chips 2019 IEEE INTERNATIONAL SYMPOSIUM ON SMART ELECTRONIC SYSTEMS (ISES 2019), 2019, : 181 - 184
- [8] HAFTA: Highly adaptive fault-tolerant routing algorithm for two-dimensional network-on-chips CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2021, 33 (21):
- [9] Cool Elevator: A Thermal-Aware Routing Algorithm for Partially Connected 3D NoCs 2016 6TH INTERNATIONAL CONFERENCE ON COMPUTER AND KNOWLEDGE ENGINEERING (ICCKE), 2016, : 111 - 116
- [10] A deadlock-free routing algorithm for irregular 3D network-on-chips with wireless links JOURNAL OF SUPERCOMPUTING, 2018, 74 (02): : 953 - 969