Comparative Evaluation of Kelvin Connection for Current Sharing of Multi-Chip Power Modules

被引:0
|
作者
Zeng, Zheng [1 ,2 ]
Li, Xiaoling [2 ]
Zhang, Xin [1 ]
Cao, Lin [3 ]
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore, Singapore
[2] Chongqing Univ, Sch Elect Engn, Chongqing, Peoples R China
[3] CRRC Yongji Elect Co Ltd, Xian, Shaanxi, Peoples R China
基金
中国国家自然科学基金;
关键词
Multi-chip power module; transient current sharing; Kelvin connection; parasitics model; CHALLENGES;
D O I
暂无
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
High-capacity power module with multiple parallel chips is a key component for renewable energy applications. Imbalance electro-thermal stresses among the parallel chips challenge the high-capacity power modules. Advanced packaging is considered as a promising solution toward higher capacity of power modules. In this paper, based on a commercial wire-bonding packaging, to enhance the current sharing in the multi-chip insulated-gate bipolar transistor (IGBT) power module, the capability of Kelvin connection to overcome the imbalance transient current and switching loss among parallel chips is comparatively surveyed. Taking parasitics into account, equivalent electric circuit and finite element analysis are proposed to illustrate the influences of Kelvin connection. Based on the customized power modules and a double-pulse test rig, simulation and experimental results are presented to comprehensively demonstrate the current sharing of parallel chips affected by Kelvin connection. It reveals the Kelvin connection can boost switching speed and reduce switching loss. However, the capability to eliminate imbalance current by using Kelvin connection is limited. Optimized direct bonded copper (DBC) layout to eliminate the asymmetric parallel loops is needed for multi-chip modules.
引用
收藏
页码:4664 / 4670
页数:7
相关论文
共 50 条
  • [21] Structural Strength and Temperature Condition of Multi-Chip Modules
    Pogalov A.I.
    Blinov G.A.
    Chugunov E.Y.
    Chugunov, E. Yu. (Chugunov-EU@inbox.ru), 2018, Pleiades journals (47) : 460 - 464
  • [22] Development of SFQ multi-chip modules for quantum bits
    Miyazaki, Toshiyuki
    Yorozu, Shinichi
    Maezawa, Masaaki
    Hidaka, Mutsuo
    Tsai, Jaw-Shen
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2007, 17 (02) : 158 - 161
  • [23] Polymer optical couplers for applications in multi-chip modules
    Ni, TD
    Sturzebecher, D
    1996 IEEE MULTI-CHIP MODULE CONFERENCE, PROCEEDINGS, 1996, : 178 - 181
  • [24] Burn-in economics model for multi-chip modules
    Alani, A
    Dislis, C
    Jalowiecki, I
    ELECTRONICS LETTERS, 1996, 32 (25) : 2349 - 2351
  • [25] INTER NEPCON - ASSEMBLY AND REPAIR OF MULTI-CHIP MODULES
    COZENS, AG
    ELECTRONIC ENGINEERING, 1969, 41 (500): : 22 - &
  • [26] DESIGN AND FABRICATION OF SILICON HYBRID MULTI-CHIP MODULES
    TRIGG, AD
    GEC JOURNAL OF RESEARCH, 1989, 7 (01): : 16 - 27
  • [27] Use of multi-chip modules in safety critical systems
    Roughton, Mike
    Hinde, Gary
    Electronic Engineering (London), 1994, 66 (809):
  • [28] An Optimized Gate-loop Layout for Multi-chip SiC MOSFFT Power Modules
    Wang, Miao
    Luo, Fang
    Xu, Longya
    WIPDA 2015 3RD IEEE WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS, 2015, : 215 - 219
  • [29] Thermally constrained placement of smart-power IC's and multi-chip modules
    Lampaert, K
    Gielen, G
    Sansen, W
    THIRTEENTH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, PROCEEDINGS 1997, 1997, : 106 - 111
  • [30] A multi-port thermal coupling model for multi-chip power modules suitable for circuit simulators
    Wang, Z. X.
    Wang, H.
    Zhang, Y.
    Blaabjerg, F.
    MICROELECTRONICS RELIABILITY, 2018, 88-90 : 519 - 523